A low dropout or LDO regulator is a DC linear voltage regulator which can operate with a comparatively small input-output differential voltage. In general, such regulators feature a comparatively low dropout voltage and a comparatively low minimum operating voltage, further having a high efficiency operation and comparatively low heat dissipation. Typically, such regulators comprise at least one field effect transistor (FET) which is typically implemented by a metal oxide semiconductor component.
Low dropout regulators are of particular interest when it comes to efficient power management in battery operated portable consumer products. The fundamental design challenge in an LDO is to stabilize it over a zero load current (no load) to a maximum load current (full load) that is required for a particular application. Moreover, LDO regulators should exhibit a stable and fast transient response to load modifications. More specifically, a transient voltage peak in a controlled output of the LDO should not exceed a maximum voltage range both during dynamic load current steps and large current spikes inherent to digital load circuitry.
Typically, LDO regulators also comprise at least one capacitor, e.g. for a dominant pole frequency compensation at the output of the regulator. A non-ideal behavior of such a capacitor can be modeled with an equivalent resistance which typically generates a zero in the loop transfer function of the LDO regulator. Crucial drawbacks of prior art solutions arise from the fact that the LDO stability critically depends on the value of the equivalent resistance, which does not only depend on the manufacturer of the capacitor but also varies with an operating frequency and temperature. The equivalent resistance of such LDO regulators therefore imposes a stability problem.